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[Other resource] FIR_1

Description: FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
Platform: | Size: 950 | Author: 李甫 | Hits:

[Other resource] two_d_fir

Description: FIR FILTER verilog code-FIR FILTER Verilog code
Platform: | Size: 26834 | Author: QQ | Hits:

[Other resource] firISPdesign

Description: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: | Size: 112475 | Author: xiong | Hits:

[Other resource] fir_finall

Description: 用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
Platform: | Size: 1233 | Author: 刘东 | Hits:

[Other resource] FIR_filter_DA_machine

Description: 用verilog 代码编写的179阶FIR数字滤波器，采用分布式算法实现-verilog code used to prepare the 179 band FIR digital filters, using Distributed Algorithms
Platform: | Size: 950 | Author: a | Hits:

[Other resource] fir2

Description: Verilog 编写的fir滤波器，可以实现fir滤波器的功能-Verilog prepared by the fir filter can achieve fir filter function
Platform: | Size: 12638 | Author: 宋南 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 基于Verilog的FIR滤波器的设计，该代码包含完整的工程，可以利用quartus软件直接运行-Design of FIR filter based on Verilog, the code contains a complete project, can use quartus software to run directly
Platform: | Size: 165888 | Author: 张林 | Hits:

[Other] Verilog-135-classic-design

Description: verilog的135个经典设计，适合初学者自学。内有FIR、数字钟、交通灯、串转并、ram、rom等等常用模块的完整verilog代码，以及测试程序。还有基本的设计源码-verilog of 135 classic design, suitable for beginners learning. There are FIR, complete verilog code for a digital clock, traffic lights, and turn string, ram, rom, etc. commonly used modules, and test procedures. There are basic design source
Platform: | Size: 116736 | Author: 王凌 | Hits:

[Software Engineering] CODE-for-FIR-filter

Description: code for FIR filter using verilog hardware descrption language
Platform: | Size: 1024 | Author: ARULKUMAR | Hits:

[assembly language] FIR

Description: This is verilog code for FIR Filter with testbench availble.
Platform: | Size: 2048 | Author: rohit | Hits:

[VHDL-FPGA-Verilog] fir

Description: This a verilog code for FIR filter works good on linux and windows platform-This is a verilog code for FIR filter works good on linux and windows platform
Platform: | Size: 1024 | Author: prad | Hits:

[matlab] fir-sample

Description: fir滤波的补码变换，用于verilog程序-fir filter complement conversion program for verilog
Platform: | Size: 2048 | Author: wq | Hits:

[VHDL-FPGA-Verilog] fir10order-verilog

Description: 1M_200k_低通fir10阶verilog标准代码-1M_200k_ order lowpass fir 10 verilog standard tags
Platform: | Size: 71680 | Author: wq | Hits:

[VHDL-FPGA-Verilog] fpga-fir

Description: 使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog language
Platform: | Size: 1404928 | Author: 韩闯 | Hits:

[VHDL-FPGA-Verilog] fir-filter

Description: 基于Verilogfir 滤波器，含低通、带通-a fir filter base on FPGA verilog software
Platform: | Size: 2048 | Author: LIU WEI | Hits:

[Other] fir

Description: A classic FIR filter implemented using Verilog HDL on the Xilinx software-A classic FIR filter implemented using Verilog HDL on the Xilinx software
Platform: | Size: 1024 | Author: DarkRofl | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyclone ii. Which includes FIR IIR FFT algorithm such as the realization of learning to image processing helpful.
Platform: | Size: 417792 | Author: 马博城 | Hits:

[VHDL-FPGA-Verilog] DDS_display

Description: 自己写的FIR八戒低通滤波器，仅供参考(Write your own FIR eight quit low-pass filter, for reference only)
Platform: | Size: 6893568 | Author: laobi_verilog | Hits:

[LabView] polyphase fir

Description: fir filter using verilog
Platform: | Size: 264824 | Author: mamine2ia | Hits:

[VHDL-FPGA-Verilog] 5_fir_tran

Description: 经典的verilog语言实现转置型FIR滤波器的代码(Code of Inverted FIR Filter Implemented by Classical Verilog Language)
Platform: | Size: 266240 | Author: ThBryan | Hits:
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